Non-volatile memory devices that are electrically programmable and erasable can be realized as flash memory devices, in which memory cells are programmed individually, but erased in blocks or pages. One type of flash memory comprises charge-trapping memory cells having a memory layer sequence of dielectric materials, in which a memory layer is arranged between confinement layers of a dielectric material having a larger energy band gap than the material of the memory layer. The memory layer sequence is located at a surface of a semiconductor body between a channel region of semiconductor material and a gate electrode that is provided to control the channel by means of an applied electric voltage. Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon (see, e.g., U.S. Pat. Nos. 5,768,192 and 6,011,725, which are both incorporated herein by reference).
In flash memory devices, blocks or pages are erased simultaneously. This means that no single bits are erased individually, but a certain number of memory cells are addressed at the same time, when an erasure is performed. As a thorough and complete erasure of all the relevant memory cells cannot be guaranteed, the erasure is usually followed by a verification step, in which single bit failures are detected and the erasing procedure is repeated, if necessary, until the erasure of all the relevant bits is verified. The repetition of the erasing procedure can be effected with increased voltages or some other modification of the operating parameters in order to secure that a complete erasure is finally obtained. This has the disadvantage that an over-erasure may occur, which leads to a decline in the endurance and data retention capability of the memory cells. The repetition of the erasing procedure causes an increase of erasing times and hence inferior write performances.